简介：Inthispaper,weproposeaneffectiveVLSIarchitectureofsub-pixelinterpolationformotioncompensationintheAVSHDTVdecoder.Toutilizethesimilararithmeticaloperationsof15lumasub-pixelpositions,threetypesofinterpolationfiltersareproposed.Asimplifiedmultiplierispresentedduetothelimitedrangeofinputinthechromainterpolationprocess.Toimprovetheprocessingthroughput,aparallelandpipelinedcomputingarchitectureisadopted.Thesimulationresultsshowthattheproposedhardwareimplementationcansatisfythereal-timeconstraintfortheAVSHDTV(1920×1088)30fpsdecoderbyoperatingat108MHzwith38.18klogicgates.Meanwhile,itcostsonly216cyclestoaccomplishonemacroblock,whichmeanstheBframesub-pixelinterpolationcanberealizedbyusingonlyonesetoftheproposedarchitectureunderreal-timeconstraints.