Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

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摘要 Inthispaper,weproposeaneffectiveVLSIarchitectureofsub-pixelinterpolationformotioncompensationintheAVSHDTVdecoder.Toutilizethesimilararithmeticaloperationsof15lumasub-pixelpositions,threetypesofinterpolationfiltersareproposed.Asimplifiedmultiplierispresentedduetothelimitedrangeofinputinthechromainterpolationprocess.Toimprovetheprocessingthroughput,aparallelandpipelinedcomputingarchitectureisadopted.Thesimulationresultsshowthattheproposedhardwareimplementationcansatisfythereal-timeconstraintfortheAVSHDTV(1920×1088)30fpsdecoderbyoperatingat108MHzwith38.18klogicgates.Meanwhile,itcostsonly216cyclestoaccomplishonemacroblock,whichmeanstheBframesub-pixelinterpolationcanberealizedbyusingonlyonesetoftheproposedarchitectureunderreal-timeconstraints.
机构地区 不详
出版日期 2008年12月22日(中国期刊网平台首次上网日期,不代表论文的发表时间)
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