摘要
Inthispaper,weproposeaneffectiveVLSIarchitectureofsub-pixelinterpolationformotioncompensationintheAVSHDTVdecoder.Toutilizethesimilararithmeticaloperationsof15lumasub-pixelpositions,threetypesofinterpolationfiltersareproposed.Asimplifiedmultiplierispresentedduetothelimitedrangeofinputinthechromainterpolationprocess.Toimprovetheprocessingthroughput,aparallelandpipelinedcomputingarchitectureisadopted.Thesimulationresultsshowthattheproposedhardwareimplementationcansatisfythereal-timeconstraintfortheAVSHDTV(1920×1088)30fpsdecoderbyoperatingat108MHzwith38.18klogicgates.Meanwhile,itcostsonly216cyclestoaccomplishonemacroblock,whichmeanstheBframesub-pixelinterpolationcanberealizedbyusingonlyonesetoftheproposedarchitectureunderreal-timeconstraints.
出版日期
2008年12月22日(中国期刊网平台首次上网日期,不代表论文的发表时间)