Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

(整期优先)网络出版时间:2008-12-22
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Inthispaper,weproposeaneffectiveVLSIarchitectureofsub-pixelinterpolationformotioncompensationintheAVSHDTVdecoder.Toutilizethesimilararithmeticaloperationsof15lumasub-pixelpositions,threetypesofinterpolationfiltersareproposed.Asimplifiedmultiplierispresentedduetothelimitedrangeofinputinthechromainterpolationprocess.Toimprovetheprocessingthroughput,aparallelandpipelinedcomputingarchitectureisadopted.Thesimulationresultsshowthattheproposedhardwareimplementationcansatisfythereal-timeconstraintfortheAVSHDTV(1920×1088)30fpsdecoderbyoperatingat108MHzwith38.18klogicgates.Meanwhile,itcostsonly216cyclestoaccomplishonemacroblock,whichmeanstheBframesub-pixelinterpolationcanberealizedbyusingonlyonesetoftheproposedarchitectureunderreal-timeconstraints.